IBM Tackles New Approach to Quantum Error Correction

IBM has unveiled a new quantum computing architecture it says will slash the number of qubits required for error correction. The advance will underpin its goal of building a large-scale, fault-tolerant quantum computer, called Starling, that will be available to customers by 2029.

Because of the inherent unreliability of the qubits (the quantum equivalent of bits) that quantum computers are built from, error correction will be crucial for building reliable, large-scale devices. Error-correction approaches spread each unit of information across many physical qubits to create “logical qubits.” This provides redundancy against errors in individual physical qubits.

One of the most popular approaches is known as a surface code, which requires roughly 1,000 physical qubits to make up one logical qubit. This was the approach IBM focused on initially, but the company eventually realized that creating the hardware to support it was an “engineering pipe dream,” Jay Gambetta, the vice president of IBM Quantum, said in a press briefing.

Around 2019, the company began to investigate alternatives. In a paper published in Nature last year, IBM researchers outlined a new error-correction scheme called quantum low-density parity check (qLDPC) codes that would require roughly one-tenth of the number of qubits that surface codes need. Now, the company has unveiled a new quantum-computing architecture that can realize this new approach.

“We’ve cracked the code to quantum error correction and it’s our plan to build the first large-scale, fault-tolerant quantum computer,” said Gambetta, who is also an IBM Fellow. “We feel confident it is now a question of engineering to build these machines, rather than science.”

IBM Unveils New Quantum Roadmap

IBM will take the first step towards realizing this architecture later this year with a processor called Loon. This chip will feature couplers that can connect distant qubits on the same chip, which is key for implementing qLDPC codes. These “non-local” interactions are what make the approach more efficient than the surface code, which relies solely on qubits communicating with their neighbors.

According to a roadmap released alongside details of the new architecture, the company plans to build a follow-on processor called Kookaburra in 2026 that will feature both a logical processing unit and a quantum memory. This will be the first demonstration of the kind of base module that subsequent systems will be built from. The following year IBM plans to link two of these modules together to create a device called Cockatoo.

The road map doesn’t detail how many modules will be used to create Starling, IBM’s planned commercial offering, but the computer will feature 200 logical qubits and be capable of running 100 million quantum operations. Exactly how many physical qubits will be required is yet to be finalized, said Matthias Steffen, IBM Fellow, who leads the quantum-processor technology team. But the new architecture is likely to require on the order of several hundred physical qubits to create 10 logical qubits, he added.

IBM plans to build Starling by 2028, before making it available on the cloud the following year. It will be housed in a new quantum data center in Poughkeepsie, N.Y., and will lay the foundations for the final system on IBM’s current road map, a 2,000 logical qubit machine codenamed Blue Jay.

IBM’s new architecture is a significant advance over its previous technology, says Mark Horvath, a vice president analyst at Gartner, who was briefed in advance of the announcement. The new chip’s increased connectivity makes it substantially more powerful and is backed up by significant breakthroughs in 3D fabrication. And if it helps IBM reach 200 logical qubits, that would bring quantum computers into the realm of solving practical problems, Horvath says.

However, Horvath adds that the modular approach IBM is banking on to get there could prove challenging. “That’s a very complicated task,” he says. “I think it will eventually work. It’s just, it’s a lot further off than people think it is.”

One of biggest remaining hurdles is improving gate fidelities across the device. To successfully implement this new architecture, error rates need to come down by an order of magnitude, admitted IBM’s Steffen, though the company is confident this is achievable. One of the main paths forward will be to improve the coherence times of the underlying qubits, which refers to how long they can maintain their quantum state. “We do have evidence that this is really one of the main bottlenecks to improving gate errors,” Steffen says.

In isolated test devices, IBM has managed to push average coherence times to 2 milliseconds but translating that to larger chips is not straightforward. Steffen said the company recently made progress with its Heron chips, going from around 150 to 250 microseconds.

Significant engineering challenges remain in supporting infrastructure as well, said Steffen, including connectors that link together different parts of the system and amplifiers. But a big advantage of the new architecture is that it requires far fewer components due to the reduced number of physical qubits. “This is one of the reasons why we’re so excited about these qLDPC codes, because it also reduces all of the nonquantum-processor overhead,” he says.

This story was updated on 10 June 2025 to correct some details of IBM’s current roadmap.